Logic Analyzer
See the timing clearly without a scope
Captures digital timing on selected GPIOs, records edge transitions at a chosen sample rate, performs preliminary decoding of common I2C / SPI / UART protocols and exports the raw capture as a standard pcap file for further analysis in Wireshark and similar tools.
A ring buffer means long low-speed captures remain reviewable: only the recent window is kept and written out in one go on export, so memory never blows up.
On-screen interface
A recreation of this page on the 2.41-inch AMOLED display (600 × 450). Actual interaction and layout follow the latest firmware.
Key capabilities
8-channel waveform
Parallel capture with per-channel toggles.
Preliminary protocol decode
I2C address and data, SPI byte streams, UART frame structure.
pcap export
A standard file format that professional tools open directly.
Ring buffer
Long captures without exhausting memory.
Technical specs
Typical scenarios
I2C troubleshooting
Confirm slave acknowledgement and whether the clock is being held low.
Custom protocol reverse engineering
Capture the full timing and analyse frame structure offline.
Teaching demos
Turn abstract timing diagrams into real, zoomable waveforms.
Related commands
page 14 Jump to the logic analyzer la start|stop Start or stop capture la dump Export pcap
- Sample rate is limited by core clock and interrupt overhead; use a dedicated logic analyzer for high-speed signals.